1. Field of the Invention
The present invention relates to a circuit for driving a power device, and particularly to a technology operable to prevent false operation of the high potential side output associated with an false signal due to the negative noise and the like at the high potential side reference potential.
2. Description of the Related Art
FIG. 9 shows a configuration of a prior driving circuit for power devices. The driving circuit is connected to a power device such as the IGBT and MOSFET (not illustrated), and used to generate a control signal to drive the power devices. Such the driving circuit is described below.
The driving circuit illustrated in FIG. 9 is equipped with a level shift circuit 10xe2x80x2, a transmitter circuit 30xe2x80x2, and a driver circuit 50. The level shift circuit 10xe2x80x2 includes resisters R1 and R2, high-voltage field effect transistors (hereafter called xe2x80x9cHNMOS transistorxe2x80x9d) T1 and T2. The transmitter circuit 30xe2x80x2 has an RS flip-flop 31, NOR gates 33 and 34, NAND gates 35 and 36, inverter gates 37 and 38, and a mask signal circuit 40c including an AND gate. The driver circuit 50 is connected to a power device such as the IGBT and MOSFET, and its output signal controls the driving of the power device.
A signal on the high potential side that controls the ON and OFF operation of the power device is fed into the level shift circuit 10xe2x80x2. The high potential side signal is a square wave signal, and is fed to the HNMOS transistors T1 and T2 of the level shift circuit 10xe2x80x2 such that a level of the high potential side signal is shifted to a high potential. The level-shifted signals (hereafter referred to xe2x80x9cON signalxe2x80x9d and xe2x80x9cOFF signalxe2x80x9d) are transmitted from the driver circuit 50 to the power device through the inverter gates 37 and 38 of the transmitter circuit 30xe2x80x2.
In general, a load of the power device driven by the driving circuit can be an inductive load of a motor or a fluorescent lamp. Owing to an influence of such an inductive load and parasitic inductance components of wiring on a printed circuit board, the high potential side reference potential (potential at the grounding line 23) in the driving circuit fluctuates to the negative side of the ground (potential at the grounding line 25) during switching, so that the high potential side signal becomes false by this fluctuation. The false signal can be generated by dv/dt applied to the high potential side reference potential or by a large negative noise level in the high potential side reference potential.
The false signal causes a current to flow through level shift resistors R1 and R2 connected to the high potential side power supply 21 by parasitic capacitance or parasitic diodes of the HNMOS transistors T1 and T2, and the like, thereby causing a voltage drop. Then the false signal is transmitted to the transmitter circuit 30xe2x80x2, resulting in false operation of the power device.
The circuit illustrated in FIG. 9 uses a logic filter technique to counteract the false operation. That is, the circuit has a mask signal circuit 40c that generates a signal that cancels the false signal. The mask signal circuit 40c generates a signal (called xe2x80x9cmask signalxe2x80x9d hereafter) that masks the xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d signals so that these signals are not transmitted to the RS flip-flop 31 if they are both active. The mask signal masks the xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d signals input to the transmitter circuit 31, that is, output signals (called xe2x80x9cmain signalsxe2x80x9d hereafter) of the NAND gates 35 and 36. At this time, the operation ranges of the main signals and the mask signal are set to the same. However when their operation ranges are dispersed, the false signal may be transmitted to the transmitter circuit 31. We now describe this situation referring to FIG. 10.
For example, suppose the case where the outputs of level shift circuit 10xe2x80x2, that is, the xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d signals rapidly decline by the influence of dv/dt and the like as shown in FIG. 10A. Also suppose that the level of the threshold values of the NAND gates 35 and 36 and the level of the threshold value for the mask signal circuit 40c are different by dispersion and the like. In FIG. 10A, the threshold values for the NAND gates 35 and 36 is illustrated by the broken line Bxe2x80x2 and the level of the threshold value for the mask signal circuit 40c is illustrated by the broken line Axe2x80x2. In this case, the main signals and the mask signal respectively vary as shown in FIGS. 10B and 10C. More particularly, the range where the mask signal is active (i.e. HIGH) becomes narrower than the range where the main signals become inactive (i.e. LOW), so that a main signal that becomes falsely inactive, i.e. a false signal, can not be sufficiently masked. Therefore, a false signal occurs in a latch input signal which is a set input signal of the RS flip-flop 31, as shown in FIG. 10D.
The present invention is aimed to solve the above problem, and its object is thus to provide a driving apparatus for driving power devices operable to securely prevent an false signal due to negative noise, dv/dt and the like on the high potential side reference potential from occurring.
A driving circuit according to the present invention is a circuit for driving a power device including level shift circuit that shifts levels of main signals comprising ON and OFF signals that respectively instruct ON and OFF of the power device and outputs the shifted signals, transmitter circuit that latches the main signals to transmit to the power device, mask signal circuit that generates a mask signal based on the main signals, the mask signal preventing the main signals from transmitting when the logic of the xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d signals becomes the same to cause false operation, and potential difference adding circuit that provides a potential difference between a signal as the main signal fed to the mask signal circuit and a signal as the main signal fed to the transmitter circuit. Therefore, the operation range of the mask signal is enlarged, and the false signal can be masked more securely, so that the occurrence of the false signal can be securely prevented.
In the driving circuit, the mask signal circuit may generate a mask signal to cancel one of the main signals from a signal obtained by inverting the other of the main signals. Therefore, it does not require to adjust with high precision threshold values, delay time, and so on of logic gate elements involved in the mask signal path and the main signals path, so that design efficiency can be improved. Further, the signal circuits can be simplified.
Further, the potential-difference adding circuit may include a resistor element, and bias current can be reduced by appropriately determining the resistance value of the resistor element. Therefore, a heat loss which is a latent problem in driving circuits can be improved.
Further, the potential-difference adding circuit may include a PMOS transistor, and the threshold voltage can be increased by using the back-gate effect. In that case, there is an advantage when the potential difference xcex94V is set at a large value.
Further, the potential-difference adding circuit may include an NMOS transistor. In that case, the potential difference xcex94V is less affected by current, so that the potential-difference value becomes more stable. Therefore, the operation range of the main signals and the operation range of the mask signal can be stably separated.
Further, the potential-difference adding circuit may include a diode. In that case, the value of the potential difference xcex94V can be more finely set with a plurality of stages of diodes.
Further, the potential-difference adding circuit may include a Zener diode. In that case, a large value of the potential difference xcex94V can be obtained with a single-stage of Zener diode, so that the layout area can be reduced.